Unpackaged semiconductor dice can be burned-in and tested prior to shipment by semiconductor manufacturers. One test procedure involves placing one or more dice in a temporary carrier. The temporary carrier provides a package for handling and electrically connecting the dice to a burn-in board or other testing equipment.
One consideration in designing temporary semiconductor carriers is the size and outline thereof. Preferably a temporary carrier has an outline, or footprint, in the x-y plane that is as small as possible. In addition, the height of a temporary carrier in the "z" direction is preferably as low as possible. With a small outline and low height, a temporary carrier can be handled by standard test equipment used for testing conventional semiconductor packages.
Another consideration in the design of temporary carriers is the ability to transmit electronic test signals to the components under test, at high speeds and with low parasitics. For example, test speeds of 500 mHz or greater are anticipated in future memory devices. In addition, the input/output capability of a temporary carrier is preferably high. This allows test procedures to be performed on components having a large number of input/output paths.
Yet another consideration in the design of temporary carriers is the ability to assemble and disassemble the temporary carriers in a production environment. Preferably a temporary carrier has the capability of being easily assembled, and reliable electrical connections made without damaging the components being tested. In addition, a temporary carrier must be capable of disassembly without damaging the components. Solder contact bumps on unpackaged dice are particularly susceptible to damage and often require a solder reflow step in order to return the bump to a shape suitable for bonding.
Another recent development in semiconductor manufacture involves packaging bare dice in "chip scale" packages. Chip scale packages are also referred to as "chip size" packages, and the dice are referred to as being "minimally packaged". Chip scale packages can also be constructed in "uncased" or "cased" configurations. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die.
Typically, a chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. For example, the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA) Alternately the external contacts can be pads arranged in a land grid array (LGA), or pins in a pin grid array (PGA).
One consideration in temporarily packaging chip scale packages for test and burn-in, is making temporary electrical connections with dense arrays of external contacts. In particular, the external contacts can vary in size between different chip scale packages, and also between external contacts on the same chip scale package. In addition, the external contacts can vary in their location along x, y and z directions. Still further, the location of the external contacts with respect to the outline of the chip scale package can also vary. Typically, "cased" chip scale packages are formed with a standard x-y-z convention which can aid in the alignment process. However, "uncased" chip scale packages can vary in peripheral size and in the locations of the external contacts.
In view of the foregoing, improved carriers for testing bumped semiconductor components including unpackaged dice, and chip scale packages are needed. In particular carriers which can be used to test either dice or packages, using standard testing equipment are needed. In addition, improved methods for aligning and electrically contacting external contacts on temporarily packaged dice and chip scale packages are needed.